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[VHDL-FPGA-Verilog] SPI

Description: 含有fifo缓冲器的SPI接口源代码，用verilog语言实现-SPI Interface fifo buffer containing the source code, using verilog language
Platform: | Size: 49152 | Author: hechunzhi99 | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: 用 Verilog语言编写的串口发送接收程序，带FIFO 已调试通过-Verilog language with sending and receiving serial program with debugging through the FIFO
Platform: | Size: 806912 | Author: 小涵 | Hits:

[VHDL-FPGA-Verilog] my_FIFO

Description: FIFO的verilog实现，成功通过验证，很好用需要的可以下载-Verilog implementation of FIFO successfully validated, the good need can be downloaded
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] rx_fifo

Description: verilog语言写的接收机FIFO，适用于xilinx环境-verilog language to write the receiver FIFO, the environment for xilinx
Platform: | Size: 5120 | Author: 刘春 | Hits:

[VHDL-FPGA-Verilog] FIFOED_UART

Description: CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
Platform: | Size: 6144 | Author: 杨胜尧 | Hits:

[VHDL-FPGA-Verilog] USB_FPGA

Description: 基于Cyclone EP3C25的USB与CY60183传递数据的FIFO Verilog HDL源代码（FPGA端程序）-The program is a communication source code about USBCyclone EP3C25 transfering data via FIFO with CY60183 (only FPGA source code(verilog HDL) is included)
Platform: | Size: 1024 | Author: lee | Hits:

[VHDL-FPGA-Verilog] fifo_4X16

Description: 完整的FIFO Verilog程序，经过仿真验证，直接可用-FIFO Verilog
Platform: | Size: 211968 | Author: 杨剑 | Hits:

[VHDL-FPGA-Verilog] fifo_verilog

Description: FIFO的verilog实现,内含PDF说明和已建好工程。-Implementation of FIFO using verilog
Platform: | Size: 744448 | Author: 孙苑 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 关于串口发送的verilog代码，实验中经常用到，已经用FIFO-it is about the uart transmit verilog code,very useful in experiment.
Platform: | Size: 3072 | Author: 李sir | Hits:

[VHDL-FPGA-Verilog] uart_1203_4

Description: MUC+fpga 串口扩展，已调试通过，4路串口共用中断，收发fifo，波特率可调，其他的可以自己添加，网上类似资料极少，极具参考价值！只提供verilog源码！-MUC+ fpga McU.that, already debugging, through, 4 road serial common interrupt, receiving and dispatching fifo, baud rate can be adjusted, the other can add your own, online similar material is few, most reference value! Provide only verilog source!
Platform: | Size: 2239488 | Author: 李康 | Hits:

[VHDL-FPGA-Verilog] System_Demons

Description: 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。 5.构造函数带参数的例子。 6.轮转仲裁的例子。 7.使用类摸板的例子。 8.如何在模块中包含子模块。 9.SystemC的Transaction级验证示例。 10.如何trace一个数组 11.SystemC中使用测试向量文件输入的例子。 12.SystemC采用UDP/TCP通信的例子。 13.Cadence的ncsc的例子。 -0 most simple SystemC program: hello, world. A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files. Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated. Delay (similar to verilog# time). In SystemC examples. 4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal. Constructor with parameters example. (6) examples of web arbitration. 7. The class Moban examples. 8 module contains a sub-module. 9.SystemC of Transaction-Level Verification example. 10 How to trace an array 11.SystemC use the example of the test vector file input. 12.SystemC using the example of the UDP/TCP communication. Examples of 13.Cadence the ncsc.
Platform: | Size: 532480 | Author: sdd | Hits:

[VHDL-FPGA-Verilog] FIFO2

Description: 用verilog HDL语言编写的fifo存储器源文件 -Using Verilog language HDL FIFO memory source file
Platform: | Size: 1481728 | Author: 王浩宇 | Hits:

[VHDL-FPGA-Verilog] afifo

Description: verilog HDL fifo , verilog HDL fifo , -verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,
Platform: | Size: 2048 | Author: shaohejiang | Hits:

[VHDL-FPGA-Verilog] fifo_uart

Description: 使用fifo完成的串口通信。verilog语言。-fifo-uart verilog
Platform: | Size: 3072 | Author: 曹曹 | Hits:

[VHDL-FPGA-Verilog] NANDFlashcontrolandFIFOcontrol

Description: 实现NAND Flash块的控制存取以及同步的FIFO的控制 verilog 代码-NAND Flash control access and control of the synchronous FIFO verilog code
Platform: | Size: 6144 | Author: alliance | Hits:

[VHDL-FPGA-Verilog] Example1

Description: fifo verilog hdl along with test bench its hardware
Platform: | Size: 3072 | Author: zakirmj | Hits:

[VHDL-FPGA-Verilog] Syn_FIFO

Description: 基于Actel公司的开发平台，verilog实现同步fifo设计-Double port ROM verilog realization, based on the development of the Actel development platform based on Actel company development platform, verilog simultaneous fifo design
Platform: | Size: 2820096 | Author: 林鸿海 | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: verilog实现的fifo到串口数据通信-verilog achieve fifo to the serial data communication
Platform: | Size: 633856 | Author: 唐华 | Hits:

[VHDL-FPGA-Verilog] versatile_fifo_latest.tar

Description: Verilog HDL语言编写的通用FIFO，让你更加了解FIFO的原理-versatile fifo based on verilog hdl.
Platform: | Size: 1293312 | Author: troy | Hits:

[VHDL-FPGA-Verilog] async_fifo

Description: 用verilog语言编写并经过综合验证的异步FIFO的源代码-the verilog code of asynchronizing fifo
Platform: | Size: 476160 | Author: 马腾宇 | Hits:
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